Tobias Alonso
Member Of Technical Staff - Research Engineer at AMD
Leinster, Ireland
Summary
👤
Senior🎓
Top SchoolTobias Alonso is an electronic engineer and research-focused FPGA specialist with a PhD in Computer Science and Telecommunications and over 10 years of experience accelerating algorithms in hardware and software. He has delivered production-grade FPGA designs for video compression, high-speed packet processing, and electronic warfare, and now develops hardware, algorithms, and tools for AI at AMD Research. Tobias blends low-level hardware design with compiler- and toolchain-level work—contributing to Xilinx’s FINN project by improving quantized neural network test coverage and export correctness—to bridge DNNs and multi-FPGA systems. Comfortable in both research and industry settings, he has a track record of automating floorplanning/resource balancing for dataflow accelerators and shipping robust interfaces between accelerators and software. Based in Leinster, Ireland, he brings a pragmatic curiosity for “interesting problems,” often finding elegant solutions that cut across hardware, algorithms, and tooling.
10 years of coding experience
3 years of employment as a software developer
PhD in Computer Science & Telecommunication Engineering Computer Hardware Engineering, PhD in Computer Science & Telecommunication Engineering Computer Hardware Engineering at Universidad Autónoma de MadridElectronic Engineering, Electronic Engineering at Universidad Nacional de San Juan
English, Spanish
Github Skills (12)
neural-network10
fpga10
quantization10
compiler10
pytorch10
machine-learning10
compiler-compiler10
dataflow-programming10
onnx10
dataflow10
python10
deep-learning9
Programming languages (6)
Github contributions (5)
Xilinx/finn
May 2020 - Mar 2021
Dataflow compiler for QNN inference on FPGAs
Role in this project:
ML Engineer
ML EngineerContributions:169 commits, 45 PRs, 20 comments in 10 months
Contributions summary:Tobias contributed to the development and testing of machine learning models, particularly those related to quantized neural network inference on FPGAs. They added test cases for the export of quantized ReLU and HardTanh activation functions to ONNX, verifying the correctness of the exported models. Furthermore, the user refactored and extended the test suite to include performance and random input tests, focusing on the multi-thresholding custom operation. These contributions directly support the FINN compiler project, improving its ability to handle a variety of quantization-aware training techniques.
dataflow-compilerfpgasinferencecompilerneural-network
hpcn-uam/LOCO-ANS-HW-coder
Apr 2021 - Feb 2022
Contributions:346 commits, 1 push in 9 months
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