Tom Riley is a Silicon Verification Engineer with 10 years' experience specializing in IP and SoC verification, formal methods, and high-speed interface debugging, including tape-outs for Microsoft's Azure Cobalt 100 and Maia 200 compute SoCs. He bridges transistor-level analog/digital design, PCB work, and RTL verification, bringing rare full-stack hardware expertise informed by research roles at the University of Waterloo and industry stints at Intel and SMART Technologies. A pragmatic engineer, he builds verification environments in UVM/SystemVerilog, authors formal assertions, and has applied generative AI tooling to accelerate verification workflows. He also ships product-grade hardware—having redesigned a PCB that reached ~5,000 units—and contributes to community tech as a makerspace board director. Based in Raleigh, NC, he’s a hardware-first engineer currently exploring web development to broaden his software toolset.
10 years of coding experience
5 years of employment as a software developer
High School, Regular/General High School/Secondary Diploma Program, High School, Regular/General High School/Secondary Diploma Program at Penetanguishene Secondary School
Bachelor of Applied Science - BASc, Electrical Engineering, Honours, Co-operative Program, Bachelor of Applied Science - BASc, Electrical Engineering, Honours, Co-operative Program at University of Waterloo
This project was created by James Oliver, Tom Riley, Ali Abdullah, and Manju Weerasinghe in 2020-2021 for the course ECE 498 at the University of Waterloo. Currently under construction.
Contributions:1 release, 58 reviews, 28 commits in 1 year 1 month
olivertomali2020-2021abdullah
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