Tommaso Marinelli
Senior R&D Engineer - Platform And Memory Modeling
Leuven, Flemish Brabant, Belgium
Summary
🤩
Rockstar🎓
Top SchoolTommaso Marinelli is a Senior R&D Engineer specializing in platform and memory modeling with 7+ years of experience in performance simulation, memory subsystems, and system-technology co-optimization. Based in Leuven, he evaluates DRAM trends, non-volatile technologies and advanced packaging using detailed gem5-driven simulations to analyze real-world workloads including generative AI on edge/mobile SoCs. He has led department-wide tool reorganization and is responsible for all gem5-related activities, contributing upstream fixes and architecture improvements to the widely used gem5 simulator. His work bridges academic rigor and industry impact—publishing multiple papers (2024–2025), mentoring students, and collaborating with universities and partners. Beyond modeling, he builds reproducible simulation flows for cache reliability and hardware fault mitigation, revealing practical trade-offs between emerging memory tech and system-level performance. Colleagues describe him as a curious, sociable technologist who pairs precise engineering with a knack for translating research into deployable evaluation frameworks.
6 years of coding experience
5 years of employment as a software developer
Doctor of Philosophy - PhD Computer Engineering, Doctor of Philosophy - PhD Computer Engineering at Universidad Complutense de MadridMaster of Science Electronic Engineering, Master of Science Electronic Engineering at Politecnico di TorinoDoctor of Philosophy - PhD Electrical Engineering, Doctor of Philosophy - PhD Electrical Engineering at KU LeuvenATHENS course Accelerator design with OpenCL, ATHENS course Accelerator design with OpenCL at Télécom ParisDiploma di maturità scientifica PNI, Diploma di maturità scientifica PNI at Liceo Scientifico Galileo Ferraris
Italian, English, Spanish
Github Skills (15)
simulations10
simulation10
open-source10
c-language10
cprogramming-language10
architectures10
simulator10
architecture10
risc-v9
sys8
software-design8
system-design8
x865
x86-645
arm4
Programming languages (3)
Github contributions (5)
gem5/gem5
Sep 2019 - May 2020
The official repository for the gem5 computer-system architecture simulator.
Role in this project:
System Architect / Software Architect
System Architect / Software ArchitectContributions:4 reviews, 5 commits, 4 PRs in 8 months
Contributions summary:Tommaso contributed to the gem5 simulator by addressing compiler errors, removing unused variables, and renaming functions to avoid naming conflicts. Their work involved modifying core system components, particularly related to memory management, and the KVM module. Additionally, they made changes to the architecture, specifically related to build configurations based on the glibc library, and introduced placeholders for system calls in the RISC-V architecture.
storedsimulationupstreamsimulatorgem5-simulator
artecs-group/gem5-artecs
Dec 2022 - Jan 2025
Contributions:11 pushes, 4 branches, 1 tag in 2 years 1 month
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