Torre Zuk
Senior Member Of Technical Staff at AMD
Calgary, Alberta, Canada
Summary
🤩
Rockstar🎓
Top SchoolTorre Zuk is a Senior Member of Technical Staff at AMD with over 30 years in software and more than two decades focused on high-performance computing, currently specializing in GPU math libraries and HIP/CUDA optimization. He drives rocBLAS and contributes to Tensile, improving numerical kernels, cross-platform build systems, and AMD ROCm compatibility—work that directly stretches GPU GEMM and tensor contraction performance. His background spans medical imaging, seismic signal processing, and real-time graphics, reflecting a rare blend of visualization, numerical algorithms, and systems engineering. Torre has led distributed international teams and shaped SDLC practices while remaining a hands-on developer who refactors kernels, handles edge-case math, and modernizes build infrastructure. Based in Calgary, he couples academic rigor (MSc/PhD coursework) with pragmatic production experience, often surfacing subtle compatibility fixes that improve performance across diverse hardware and OS environments.
6 years of coding experience
21 years of employment as a software developer
BSc, Computer Science, BSc, Computer Science at University of AlbertaMSc, Computer Science, MSc, Computer Science at The University of British ColumbiaPhD, Computer Science, PhD, Computer Science at University of Calgary
Github Skills (18)
assembly10
c-language10
computation10
numerical10
amd10
hip10
numerics10
gpu10
performance-optimization10
cprogramming-language10
numeric10
auto-tuning9
python9
testing8
cuda7
Programming languages (5)
Github contributions (5)
ROCm/rocBLAS
Aug 2019 - Jan 2023
Next generation BLAS implementation for ROCm platform
Role in this project:
Backend Developer
Backend DeveloperContributions:116 reviews, 439 commits, 219 PRs in 3 years 5 months
Contributions summary:Torre's commits primarily focus on implementing and refining mathematical functions within the rocBLAS library. Their contributions include handling negative and small batch counts for `asum` and `nrm2` functions, adding shift parameters, and exposing templates. The user refactored code, added new kernels and improved existing ones, demonstrating a focus on numerical computation and optimization within the rocBLAS framework. These commits also incorporate test-related updates, and the user also has a clear understanding of API interfaces.
blasnext-generationrocmhip
ROCm/Tensile
Sep 2019 - Nov 2022
Stretching GPU performance for GEMMs and tensor contractions.
Role in this project:Back-end Developer & Performance Engineer
Back-end Developer & Performance EngineerContributions:114 reviews, 32 commits, 45 PRs in 3 years 3 months
Contributions summary:Torre primarily contributed to the Tensile library by modifying and updating build processes and dependencies to support AMD's ROCm platform. Their work includes fixing compiler warnings, incorporating updates for Windows support, and adapting to changes in HIP (Heterogeneous-Compute Interface for Portability) headers, specifically related to deprecated includes and API changes. The user also focused on integrating and parsing HIPCC version information and adapting compilation flags for differing HIPCC versions and operating systems, thereby improving the library's compatibility and performance on different AMD hardware setups.
amdpythontensorhipauto-tuning
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.