Torsten Meissner
Software Engineer
Dresden, Saxony, Germany
Summary
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RockstarTorsten Meissner is an experienced FPGA engineer and software engineer based in Dresden with 13 years designing and verifying FPGA firmware using VHDL, SystemVerilog, PSL/SVA and modern verification frameworks like OSVVM and VUnit. He combines deep RTL expertise with practical test automation skills, contributing QA-focused tests to the well-known GHDL VHDL simulator—adding PSL feature coverage and addressing subtle numeric and built-in function issues. Comfortable across the toolchain, he maintains Make- and container-based build systems and programs microcontrollers, bridging low-level firmware with reproducible build and CI practices. Torsten’s work emphasizes verification rigor and portability, ensuring designs are both formally checked and practically testable. His blend of hands-on simulation test development and firmware engineering makes him a strong asset for teams needing robust, verifiable FPGA solutions.
13 years of coding experience
German, English
Stackoverflow
31reputation
3kreached
3answers
0questions
Github Skills (14)
simulator10
test-automation10
vhdl10
testing9
ghdl9
testbench9
compiler-compiler8
compiler8
code-coverage6
fpga6
modelsim6
formal-verification6
psl6
questasim6
Programming languages (6)
Github contributions (5)
ghdl/ghdl
Sep 2019 - Dec 2022
VHDL 2008/93/87 simulator
Role in this project:
QA Engineer / Test Automation Engineer
QA Engineer / Test Automation EngineerContributions:10 reviews, 24 commits, 20 PRs in 3 years 3 months
Contributions summary:Torsten's contributions primarily focus on adding and modifying test cases for the GHDL VHDL simulator. They introduced tests for PSL (Property Specification Language) features, including assertions, assumptions, and cover directives. Additionally, the user added tests for built-in PSL functions such as `stable()`, `rose()`, and `fell()`. They also addressed issues related to specific functionalities, like numeric_std_unsigned operations, through testing.
vhdlsimulationghdlcompilersimulator
tmeissner/libvhdl
Nov 2014 - May 2022
Library of reusable VHDL components
Contributions:146 commits, 4 PRs, 83 pushes in 7 years 7 months
modularityvlsireusablevhdlassertions
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