Tsukasa OI
Research Engineer at Freelance (Self-employed)
Toshima, Japan
Summary
🤩
Rockstar🎓
Top SchoolTsukasa OI is a research engineer based in Toshima, Japan with 14 years of hands-on experience in virtualization, rootkit analysis, and reverse engineering. He combines industry research roles and long-running independent security work, currently contributing at TRASIO while maintaining active freelance research. His open-source contributions span low-level systems projects—from hardening x86 CPUID detection in autoconf-archive to extending ebtables integration in firewalld and adding RISC-V ISA extensions to the Spike simulator—demonstrating deep familiarity with CPU architecture and emulator internals. Colleagues rely on him for pragmatic, security-focused fixes that improve platform correctness and tooling for emerging ISAs. Notably, his work often targets subtle parser and detection logic, reducing obscure failure modes in toolchains and simulators. He trained in electronic and information engineering and brings a researcher’s curiosity to production-grade back-end code.
14 years of coding experience
5 years of employment as a software developer
(none), Electonic and Information Engineering, (none), Electonic and Information Engineering at Suzuka National Collage of Technology
Japanese, English
Github Skills (28)
assembly10
c-language10
system-programming10
qemu10
compiler-development10
autoconf10
risc-v10
firewall10
c1110
autotools10
gcc10
iptables10
c1710
assemble10
assembler10
Programming languages (17)
Github contributions (5)
autoconf-archive/autoconf-archive
Jan 2012 - Aug 2014
A mirror of the GNU Autoconf Archive, a collection of more than 500 macros for GNU Autoconf that have been contributed as free software by friendly supporters of the cause from all over the Internet.
Role in this project:
Back-end Developer
Back-end DeveloperContributions:7 commits in 2 years 7 months
Contributions summary:Tsukasa's contributions primarily involve modifying and improving the `autoconf-archive` project, which is a collection of macros for GNU Autoconf. They focused on enhancing the existing macros, particularly those related to CPU architecture detection and compiler flag generation, specifically for Intel and AMD processors. The work includes fixing bugs in CPU detection and adding support for new Intel compiler versions. The user's changes included refactoring and hardening the x86 CPUID pattern matching logic.
unixmacrossystem-programmingportabilitycause
riscv-software-src/riscv-isa-sim
Nov 2021 - Dec 2021
Spike, a RISC-V ISA Simulator
Role in this project:Back-end Developer
Back-end DeveloperContributions:12 reviews, 6 commits, 6 PRs in 21 days
Contributions summary:Tsukasa primarily contributed to the RISC-V ISA simulator by adding support for specific extensions and instructions. Their work involved modifying the `processor_t::parse_isa_string` function to accept dummy extensions like "Zifencei" and "ZiHintPause," preventing unsupported extension errors. The user also implemented changes to the `parse_varch_string` and `parse_isa_string` functions, using `strtolower` and C-style strings, respectively, which refactored the parsing logic. Furthermore, they added support for the "Zfhmin" extension, including modifications to the `processor.cc` and `.h` files as well as modifications to relevant instruction files (e.g., fcvt_h_s.h). The user also added disassembler support for the unimp instruction.
risc-visariscvriscv32simulator
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