Tsung-tso Hsieh is a software engineer with nine years of industry and research experience, currently developing high-performance Verilog compile and simulation tooling at 新思科技. He holds a master’s (4.0/4.3 GPA) and bachelor’s double major in Computer Science and Law from 國立清華大學, where he also contributed a Kubernetes-aware GPU scheduler for elastic distributed deep learning (VodaScheduler). His background spans embedded real-time firmware, algorithm design, and introducing ML-driven automation that reduced manual analysis effort by 90% during an internship at 聯發科. Comfortable bridging research and production, he brings strengths in systems-level programming, performance optimization, and practical open-source engineering. Based in Hsinchu with ties to both Taiwan academia and Canadian residency, he blends rigorous academic training with hands-on delivery in semiconductor and ML infrastructure domains.
9 years of coding experience
2 years of employment as a software developer
Bachelor's degree, Double Major in Computer Science and Law, Bachelor's degree, Double Major in Computer Science and Law at 國立清華大學
GPU scheduler for elastic deep learning workloads in Kubernetes cluster
Contributions:2 releases, 7 reviews, 200 commits in 1 year 7 months
containerspytorchschedulinghorovodworkloads
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