Tsvi Mostovicz is a Design Verification Engineer with five years of focused experience in SoC verification, UVM methodology, and CAD automation, currently driving verification at Intel. He has a proven track record building UVM-based environments from scratch for complex ARM and mixed-architecture debug subsystems and leading CI/CD, Ansible, and Docker initiatives to modernize verification flows. At RAD Data Communications he spearheaded CI pipelines, Git migrations, automated regression and coverage reporting, and presented tools at CDNLive Israel, blending hands-on verification with DevOps rigor. Tsvi pairs deep protocol and simulation expertise with practical infrastructure work—standardizing simulation farms and moving documentation into Git-backed MkDocs—to make teams more reproducible and auditable. He began his career in hardware testing and Linux systems administration, which gives him an unusual steadiness troubleshooting across software, tools, and silicon. Based in Meitar, Israel, he brings methodological discipline and a history of turning legacy toolchains into maintainable, automated workflows.
4 years of coding experience
10 years of employment as a software developer
Yeshivat Kerem BeYavne
B.Sc., Electrical Engineering, B.Sc., Electrical Engineering at Lev Academic Center (JCT) (Jerusalem College of Technology )
Sciences, Sciences at Yeshiva Tichonit - Yavne, Antwerpen
:house_with_garden: Open source home automation that puts local control and privacy first.
Contributions:1 review, 1 comment in 3 months
raspberry-pipythonhouseprivacy-firstasyncio
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