Tymoteusz Blazejczyk is a DevOps and FPGA/embedded systems engineer with 11 years’ experience designing high-speed, low-latency hardware accelerations and production-grade firmware for data-center and telecom applications. He blends RTL, software and verification expertise (SystemVerilog, SystemC, C/C++, Rust, Go, Python) with modern DevOps practices—CI/CD, containerized builds, co-simulation and QEMU-based emulation—to automate full FPGA and embedded lifecycles. At Intel and other employers he delivered multi-100Gb/s networking solutions, virtualization-aware drivers and scalable verification frameworks, and has repeatedly modernized CI pipelines for FPGA projects. Comfortable both as an individual freelancer and in multidisciplinary teams, he architects end-to-end systems from requirements through validation, including analog and PCB considerations. Based in Eindhoven and open to remote or local Gdańsk roles, he brings a practical knack for mixing high-level languages with HDL for faster co-simulation and iteration cycles. His background shows a pattern of pushing FPGA workflows toward software development best practices, making hardware development more reproducible and automatable.
11 years of coding experience
12 years of employment as a software developer
Bachelor's Degree Electronics Engineering, Bachelor's Degree Electronics Engineering at Gdańsk University of Technology
Contributions:1 PR, 234 pushes, 1 branch in 2 months
cpptestingunitembedded-devicesunit-tests
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