Udi Finkelstein - Staff Engineer at Arm

Udi Finkelstein

Staff Engineer at Arm

Israel

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Summary

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Senior

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Udi Finkelstein is a Staff Engineer with 12+ years of hands-on experience across ASIC/FPGA design, embedded software, and system-level architecture, now at Arm after a long tenure driving RTL and silicon for Sony’s AI/DNN products. He blends deep hardware expertise (RTL, formal verification, CPU register infra) with strong software skills in C/C++, Python, and embedded Linux, making him a true full-stack hardware/software engineer. Udi has owned key blocks on high-performance routers and next-gen AI silicon, created tooling for post-silicon debug, and evangelized open-source CAD workflows to accelerate development. His open-source contributions to prominent projects like Yosys and slang show a focus on SystemVerilog semantics and compiler/tooling compatibility, while Android work on AntennaPod highlights versatility across domains. He holds advanced engineering degrees from Tel Aviv University and Technion and a career habit of turning complex architecture problems into pragmatic, verifiable implementations. A less obvious strength: he repeatedly bridges vendor-specific legacy flows with modern toolchains, making legacy designs more maintainable and portable.

11 years of coding experience

35 years of employment as a software developer

Msc MBA, Msc MBA at Technion - Israel Institute of Technology

Bsc Electrical Engineering, Bsc Electrical Engineering at Tel Aviv University

Stackoverflow

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Github Skills (20)

verilog10

parser10

systemverilog10

yosys10

java10

javas10

compiler-design10

compiler-compiler10

parsing10

parse10

android10

compiler10

c-language9

parserator9

open-source9

Programming languages (17)

C#JavaC++CRustMakefileScalaGo

Github contributions (5)

YosysHQ/yosys

Sep 2017 - Sep 2020

Yosys Open SYnthesis Suite

Role in this project:

Full-stack Developer

Contributions:1 review, 27 commits, 15 PRs in 3 years

Contributions summary:Udi primarily contributed to the Yosys Open SYnthesis Suite by implementing and refining SystemVerilog system functions, specifically `$size()`, `$bits()`, `$high()`, `$low()`, `$left()`, and `$right()`. The user's work involved modifying the frontends to correctly parse, simplify, and evaluate these functions, including handling array slices and multidimensional arrays. They also added support for SystemVerilog syntax and corrected issues related to incorrect assignments and declaration syntax.

synthesispythonsuiteyosys

MikePopoloski/slang

Aug 2022 - Dec 2022

SystemVerilog compiler and language services

Role in this project:

Backend Developer

Contributions:38 reviews, 5 commits, 18 PRs in 3 months

Contributions summary:Udi focused on enhancing the SystemVerilog compiler and language services. They implemented features to parse legacy vendor workflows and added command-line options for handling vendor-specific commands, including ignoring or renaming them. The user also introduced new command-line options such as `--exclude-ext` and `--ignore-directive`, along with the `--allow-redefinition` flag, which indicates active development efforts to extend functionality and compatibility. These changes involved modifications to the `CommandLine` and `Driver` classes and also included the refactoring of the `DuplicateDefinition` error to become a warning in some contexts.

uvmsystemveriloglanguage-servicecompilervlsi

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