Uma Rajagopalan
Design Verification Engineer
Karnataka, India
Summary
👤
Senior🎓
Top SchoolUma Rajagopalan is a Design Verification Engineer with over 10 years at IBM specializing in processor and SoC functional verification, CAPI/OpenCAPI enablement, and post-silicon validation. She has deep experience validating communication protocol IPs and enabling customer systems, blending hands‑on verification with system-level troubleshooting. A PMP-certified project manager early in her career, she brings structured delivery and customer-facing program management to complex hardware projects. Based in Karnataka, India, Uma’s background spans hardware design, research at IIT, and long-term contributions to processor I/O enablement, giving her a rare mix of verification rigor and practical deployment experience.
10 years of coding experience
18 years of employment as a software developer
BTech, Biomedical/Medical Engineering, 72.3, BTech, Biomedical/Medical Engineering, 72.3 at Model Engineering College
Github Skills (6)
simulator9
verify9
simulation9
service-layer9
co-simulation8
acceleration3
Programming languages (1)
Github contributions (2)
OpenCAPI/ocse
Jan 2017 - Sep 2021
OpenCAPI Simulation Engine. Used to verify application and acceleration development(s) using a co-simulation environment
Contributions:71 commits, 2 PRs, 7 pushes in 4 years 8 months
accelerationsimulationsimulation-engineverifysimulator
ibm-capi/pslse
Apr 2016 - Sep 2021
Power Service Layer Simulation Engine
Contributions:43 commits, 1 PR, 42 pushes in 5 years 6 months
simulationsimulation-enginesimulatorpowerservice-layer
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