Summary
Umesh Bhaskar is a Senior CPU Simulation Architect with 13 years of experience in computer architecture, performance modeling, and digital VLSI design, currently driving CPU simulation work at NVIDIA. He built and maintained architectural models and led performance analysis for next-generation CPUs at Qualcomm, including a C++/SystemC SMMU performance model and extensive gem5-based exploration. Skilled in Python, C++, Java, Verilog and wireless DSP, he bridges low-level RTL/ASIC design with high-level architectural trade-offs to improve throughput and system performance. His background includes wireless modem and spectrum-sensing work, giving him a practical edge in system-level modeling where radio and compute interact. Based in California with an M.S. in Computer Engineering from UC Santa Barbara, he combines rigorous academic training with hands-on implementation of bit-accurate and cycle-accurate models.
13 years of coding experience
15 years of employment as a software developer
Bachelor of Engineering, Electronics and Communication, Bachelor of Engineering, Electronics and Communication at Visvesvaraya Technological University
Machine Learning Engineer Nanodegree, Machine Learning, Machine Learning Engineer Nanodegree, Machine Learning at Udacity
Master of Science (M.S.), Computer Engineering, Master of Science (M.S.), Computer Engineering at UC Santa Barbara