Umesh Rao is a Principal Engineer based in Santa Barbara with over two decades of experience in semiconductor and image processing systems, combining deep expertise in FPGA/ RTL implementation with algorithm development for HDR, tone mapping and thermal imaging. Trained at IIT Delhi and Case Western Reserve and more recently in Learning Design and Technology from the University of Hawaii, he uniquely bridges hardware engineering and human-centered learning practices. His work spans Intel, ON Semiconductor, Aptina, FLIR and Alcon, where he’s led rapid prototyping from MATLAB to VHDL, filed a provisional patent on thermal image shading correction, and optimized real-time image pipelines. Umesh pairs a systems-engineering mindset with hands-on HDL coder HLS workflows to deliver production-ready silicon and FPGA solutions. He is motivated by lifelong learning as an organizational health metric and applies instructional design principles to technical mentorship and cross-disciplinary problem solving. Colleagues see him as the engineer who becomes a student when faced with a complex problem—fast to learn, iterate, and bring solutions to silicon.
9 years of coding experience
19 years of employment as a software developer
Master of Education (M.Ed.) Learning Design and Technology, Master of Education (M.Ed.) Learning Design and Technology at University of Hawaii at Manoa
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