Valerio Lanieri
Lead Design Engineer at Cadence
Antibes, Provence-Alpes-Côte d'Azur, France
Summary
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Senior🎓
Top SchoolValerio Lanieri is a lead design engineer with eight years of focused experience in standard cell design and verification across advanced nodes, now leading design work at Cadence after senior roles at Arm. He combines hands-on layout, Liberty generation and STA/SPICE correlation with automation projects—building tools for MIMCAP extraction and EDA view flows that sped multi-node deliveries from 5nm down to 2nm. Valerio has deep expertise in automotive and high-performance platforms, notably QA on 40nm automotive libraries and Monte Carlo-backed correlation for 2nm libraries, plus custom cell work to resolve congestion and timing on core issue queues. Trained at Politecnico di Torino, Télécom Paris and EURECOM, he pairs rigorous academic credentials with a knack for reverse-engineering that informs pragmatic, manufacturable designs. Based in Antibes, he’s as comfortable tuning process-sensitive knobs for silicon signoff as he is scripting automation to remove repetitive pain points.
8 years of coding experience
6 years of employment as a software developer
MSc in Electronic Engineering, MSc in Electronic Engineering at Télécom ParisHumanities/Humanistic Studies, 93/100, Humanities/Humanistic Studies, 93/100 at Liceo Classico Pontano SansiMSc in Electronic Engineering, Smart Objects, MSc in Electronic Engineering, Smart Objects at EURECOMMaster of Science - MS, Electronic Engineering, 110 cum laude, Master of Science - MS, Electronic Engineering, 110 cum laude at Politecnico di Torino
English, Italian, French, Spanish, PortugueseGithub contributions (5)
cold-ice/hwsec
Jul 2018 - Apr 2019
Contributions:3 commits, 4 pushes, 1 branch in 9 months
cold-ice/Butterfly
Dec 2017 - May 2019
Contributions:3 pushes, 1 branch in 1 year 4 months
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