Varun Saxena
Senior CPU Design Engineer at Apple
California, United States
Summary
🤩
Rockstar🎓
Top SchoolVarun Saxena is a Senior CPU Design Engineer at Apple with five years of hands-on experience in CPU/GPU microarchitecture, RTL design, and EDA tool development. He earned an MS in ECE from Georgia Tech after a distinguished BE (Honors) from NSIT, and has led research and RTL implementation of a rasterization engine for the Vortex GPGPU while guiding a team in HPArch lab. Before Apple he owned and shipped multiple EDA tools and flows at Texas Instruments—improving runtimes, automating sign‑off, and building GUI-driven verification pipelines—and interned on verification and stimulus-generation projects at NVIDIA and Apple. Varun blends practical silicon-centric verification expertise with academic research in vector and graphics engine extensions, optimizing power-performance-area tradeoffs. He is based in California and is known for translating complex architectural ideas into production-ready RTL and scalable verification frameworks.
5 years of coding experience
5 years of employment as a software developer
Bachelor of Engineering (B.E.-honors) Electrical Electronics and Communications Engineering, Bachelor of Engineering (B.E.-honors) Electrical Electronics and Communications Engineering at Netaji Subhas Institute of TechnologyMaster of Science - MS Electrical and Computer Engineering, Master of Science - MS Electrical and Computer Engineering at Georgia Institute of Technology12th Science, 12th Science at Navy Children School
English, HindiProgramming languages (2)
Github contributions (5)
varunsax12/single_cycle_mips
Feb 2021 - Jul 2022
Contributions:3 pushes, 1 branch in 1 year 4 months
varunsax12/pipeline_mips
Feb 2021 - Oct 2021
Contributions:3 pushes, 1 branch in 7 months
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