Summary
Venkatesh Arunachalam is an experienced analog and mixed-signal IC designer with nine years in advanced SerDes, equalization (DFE, CTLE), PLL/DLL and clocking solutions, currently working as an MTS Analog Design Engineer at AMD in Milpitas. He has a strong track record designing high-speed SerDes receivers (including 28 Gbps projects in 10FF/20nm) and low-EMI PLL clock generators from roles at Oracle, Sun Microsystems and Alliance Semiconductor. Venkatesh pairs hands-on circuit implementation skills with deep familiarity of industry IC design toolflows, enabling robust performance tuning across process nodes. Trained with an M.S. in Electrical and Computer Engineering from UMass Amherst and a B.E. from Bangalore University, he brings both academic rigor and practical system-level insight to complex mixed-signal challenges. Notably, his career reflects repeated success moving designs from concept to silicon in both SOC and discrete clocking contexts.
9 years of coding experience
13 years of employment as a software developer
Bengaluru University
Masters, Electrical and Computer Engineering, Masters, Electrical and Computer Engineering at University of Massachusetts Amherst