Victor Benarbia is a Principal Design Automation Engineer with 13 years at Arm, specializing in automating hardware production pipelines and building software that tackles RTL and validation challenges across physical IP to very large system interconnects. He has played a key role on cutting-edge interconnect products (CoreLink CMN/Neoverse) used in platforms like AWS Graviton, blending deep semiconductor engineering roots from Polytech Marseille with pragmatic software design. Known for turning complex hardware verification and integration needs into scalable automation, he thrives on bridging low-level RTL constraints with modern tooling and CI-driven flows. Based in Leander, Texas, he brings a decade of focused automation experience and a preference for practical, high-impact solutions that accelerate silicon delivery.
13 years of coding experience
13 years of employment as a software developer
Engineer's degree, Semiconductor and Telecommunication, Engineer's degree, Semiconductor and Telecommunication at Polytech'Marseille
engineer, microelectronics, engineer, microelectronics at Polytech Marseille
Contributions:1 release, 1 review, 67 commits in 2 years 2 months
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