Victor Besyakov
Senior Principal Engineer at Marvell Technology
Ottawa, Ontario, Canada
Summary
👤
Senior🎓
Top SchoolVictor Besyakov is a Senior Principal Engineer and veteran ASIC design verification specialist with over 25 years in hardware and verification roles and nine years in focused verification practice. He has led and executed complex verification projects across startups and major semiconductor firms, currently shaping verification strategy at Marvell while running IC Verimeter for EDA R&D and open-source tools. His background spans hands-on simulation, team leadership, and contractor-to-principal transitions at companies including Untether AI, Qualcomm Atheros, AMD, and Ciena, reflecting deep IP and system-level verification expertise. Victor combines formal engineering rigor from an MS in Electrical Engineering with practical, entrepreneurial fluency—building verification frameworks and contracting businesses that bridge research and product delivery. Not obvious from titles alone, he maintains active EDA R&D and open-source work that informs his production verification approaches, keeping him current with emerging flows and toolchains. Based in Ottawa, he brings a rare blend of long-term industry perspective and continued hands-on engineering leadership in ASIC verification.
9 years of coding experience
23 years of employment as a software developer
Ms, Electrical engineering, Ms, Electrical engineering at Samara State Technical University
Github Skills (23)
verilog10
systemverilog10
python10
dpi10
ip10
systemc10
verilator10
asic10
socket10
tcp10
cpp10
tcp-socket10
open-source9
system9
c-library6
Programming languages (4)
Github contributions (5)
xver/Shunt
Oct 2016 - Jan 2023
SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
Contributions:14 releases, 1020 commits, 3 PRs in 6 years 4 months
pythonsocketsystemcsystemverilogtcp
xver/dist_sim
Oct 2019 - Jul 2023
Contributions:8 pushes, 1 branch in 3 years 9 months
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