Victor Raposo
Software Engineer II at Cadence
Rio de Janeiro, Brazil
Summary
👤
Senior🎓
Top SchoolVictor Raposo is a Software Engineer II with a decade of experience blending electronics and software, currently working at Cadence in Rio de Janeiro while pursuing a master’s in Electrical Engineering at UFRJ. His background spans analog and digital CMOS integrated circuit research—designing a multi-process CMOS image sensor, running Monte Carlo analyses in Cadence Virtuoso, and accelerating simulations with Verilog-A replacements. He pairs hands-on layout verification (DRC/LVS/extracted parasitics) with scripting in Python and MATLAB to automate result analysis, reflecting a strong systems-to-tooling mindset. Recognized with competitive scholarships (CNPq and FAPERJ Nota 10), he moves fluidly between research and product validation, bringing practical validation rigor to software and EDA workflows.
10 years of coding experience
1 year of employment as a software developer
Masters, Electrical Engineering, 3,0/3,0, Masters, Electrical Engineering, 3,0/3,0 at UFRJ - Federal University of Rio de JaneiroEnsino Médio, Ensino Médio at Colégio Técnico da Universidade Rural
Github Skills (3)
knockoutjs1
rpg1
azerothcore1
Programming languages (2)
Github contributions (5)
VRavaglia/apostila-eletronica-1-erros
Nov 2018 - Jan 2021
Contributions:2 pushes, 1 branch, 32 issues in 2 years 1 month
VRavaglia/LingProg-2019-1-Trabalho
Apr 2019 - Nov 2019
Contributions:1 release, 47 pushes, 1 tag in 7 months
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