Victor Ying
Senior Engineer, Future-Gen RISC-V CPU Architecture at Tenstorrent Inc.
Cambridge, Massachusetts, United States
Summary
👤
Senior🎓
Top SchoolVictor Ying is a senior engineer specializing in future-generation RISC-V server CPU architecture, bringing 11 years of experience spanning computer architecture, parallelizing compilers, and parallel programming models. Currently at Tenstorrent he leads evidence-based roadmapping to build high-performance server CPUs, building on a PhD and research tenure at MIT CSAIL where he designed multicore microarchitectures and led LLVM/Clang compiler work for massively parallel hardware. His internships at Microsoft and NVIDIA focused on MLIR-based distributed-GPU compilation and analytical modeling for ML workloads, respectively, linking processor design to real-world ML system needs. Victor combines deep hardware-software co-design expertise with practical tooling experience (from firmware and Python tools to compiler extensions), and is driven by making processors easier for programmers to extract performance and efficiency. Based in Cambridge, MA, he runs victorying.com and maintains a focus on building high-performance CPUs that bridge academic research and deployable products.
11 years of coding experience
1 year of employment as a software developer
Doctor of Philosophy - PhD, Electrical Engineering and Computer Science, Doctor of Philosophy - PhD, Electrical Engineering and Computer Science at Massachusetts Institute of TechnologyRichard Montgomery High SchoolBachelor of Science in Engineering (B.S.E.) summa cum laude, Electrical Engineering, 3.94/4.00, Bachelor of Science in Engineering (B.S.E.) summa cum laude, Electrical Engineering, 3.94/4.00 at Princeton University
English
Stackoverflow
1reputation
0reached
0answers
0questions
Github Skills (100)
authentication10
sms10
factor10
tapir10
cilk10
r9
vagrant9
hugo-theme9
ruby9
security9
cilkplus9
clang9
auth9
page-builder9
2factor9
Programming languages (9)
Github contributions (5)
SwarmArch/T4
Apr 2020 - Jul 2021
Code released to accompany the ISCA paper: "T4: Compiling Sequential Code for Effective Speculative Parallelization in Hardware"
Contributions:1 review, 6 commits, 1 PR in 1 year 2 months
iscaeffectivereleasedhardwareparallelization
SwarmArch/sim
May 2020 - Feb 2023
ordspecsim: The Swarm architecture simulator
Contributions:3 commits, 4 PRs, 5 pushes in 2 years 8 months
simulatorarchitectureswarmsimulation
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