Vighnesh Iyer
Berkeley, California, United States
Summary
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Rockstar🎓
Top SchoolVighnesh Iyer is a hardware verification and design researcher with 12 years of experience bridging academic research and industry internships across Berkeley, NVIDIA, Apple, Google, and Jane Street. He specializes in dynamic verification techniques, assertion synthesis, hardware design languages (Chisel), and applying machine learning to improve DV productivity and coverage. At UC Berkeley he built high-performance testbench APIs and fuzzing tools, and contributed backend work to Berkeley’s prominent Gemmini systolic-array project by extending Chisel mesh and PE logic and automated matrix tests. His background spans RTL coverage prediction, FPGA emulation, fault injection platforms, and CPU verification, giving him a pragmatic view of both silicon and tooling gaps. Based in Berkeley, he combines deep verification theory with hands-on implementation experience that often surfaces in scalable test generation and synthesis work.
12 years of coding experience
11 years of employment as a software developer
Bachelor of Science (BS), Electrical Engineering and Computer Science, Bachelor of Science (BS), Electrical Engineering and Computer Science at University of California, Berkeley
Spanish
Stackoverflow
33reputation
6kreached
3answers
2questions
Github Skills (14)
hardware-designs10
asic10
accelerator10
chisel10
testing9
matrix-multiplication9
mql6
ios6
php6
laravel6
indicator6
metatrader6
security6
python4
Programming languages (13)
Github contributions (5)
ucb-bar/gemmini
Nov 2018 - Jul 2019
Berkeley's Spatial Array Generator
Role in this project:
Back-end Developer
Back-end DeveloperContributions:33 commits, 18 pushes in 8 months
Contributions summary:Vighnesh primarily contributes to the development and testing of a systolic array, which is an ASIC accelerator. Their work involves modifying and creating Chisel code (a hardware description language) for the mesh and PE (Processing Element) components. The user also focuses on generating tests for matrices of varying sizes, demonstrating an understanding of hardware design and verification. They have implemented functions for generating the A, B, and S matrices.
asicarrayspatialjuliaberkeley
EECS150/fpga_labs_fa19
Aug 2019 - Oct 2019
FPGA lab skeleton files and specs for EECS 151/251A Fall 2019
Contributions:97 commits, 91 pushes, 1 branch in 1 month
eecsfallskeletonspecs2019-fall
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