Vijaya Bhaskar is a Technical Lead Engineer with six years focused on pre-silicon validation and a broader 15+ year track record in ASIC and system verification across Intel and other semiconductor firms. At Intel she leads CXL cache/memory validation for Xeon Diamond Rapids, built a reusable checker framework, and designed stress tests that surfaced complex coherence and memory-performance issues. Previously she drove validation for Optane DC persistent memory controllers and implemented scalable verification strategies that accelerated RTL bug discovery and resolution. Known for strong triage and root-cause skills, she pairs deep protocol-level expertise with practical test infrastructure design. Based in Hillsboro, Oregon, she blends hands-on engineering with ML research interests noted on her GitHub, bringing a research-informed approach to production verification challenges.
6 years of coding experience
13 years of employment as a software developer
B.E(Hons), Electrical & Electronics, B.E(Hons), Electrical & Electronics at Birla Institute of Technology and Science
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