Vimarsh Sathia is an associate researcher and compiler engineer with 8 years of experience focused on compiler infrastructure for ML and dataflow architectures. Currently at AMD, he works on MLIR-driven tooling for dataflow targets after a stint at Qualcomm contributing to IREE and tiling optimizations and earlier engineering roles at Microsoft. He holds a PhD in Computer Science from UIUC and a BTech from IIT Madras, blending deep academic research with practical systems work. Vimarsh’s toolkit spans compiler design, MLIR, and performance-focused code generation, and he brings a knack for turning research prototypes into production-ready compiler passes. An Urbana-based engineer, he pairs rigorous theory with hands-on implementation, often exploring the intersection of ML compilers and hardware-aware optimization.
7 years of coding experience
1 year of employment as a software developer
Indian Institute of Technology Madras
Grade 10, Grade 10 at Hiranandani Foundation School
Grade 12, Grade 12 at Smt.Sulochanadevi Singhania School
Doctor of Philosophy - PhD, Computer Science, Doctor of Philosophy - PhD, Computer Science at University of Illinois Urbana-Champaign
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