Vinayaka Raju is a Senior Design Verification Engineer based in Bengaluru with eight years of experience verifying consumer electronics chips using SystemVerilog, UVM and Assertion Based Verification. He combines a strong academic foundation—MTech in VLSI and Embedded Systems from PES University—with practical scripting fluency in Perl to automate and accelerate verification flows. At a confidential employer since 2016 he has driven complex verification projects from testbench architecture to coverage closure, balancing rigor with pragmatic delivery. Known for a methodical approach, he quietly experiments with improving engineering productivity (his GitHub tagline hints at an ongoing effort to write better software).
8 years of coding experience
Pre University, Pre University at Admissions Open 2018 | St.Claret College
Electronics and Communication Engineering, Electronics and Communication Engineering at East West Institute Of Technology
Mtech, VLSI and Embedded System, Mtech, VLSI and Embedded System at PES University
Contributions:17 commits, 15 pushes, 1 branch in 7 months
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