Vincent Illionnet is an ingénieur chercheur based in Paris with roughly two years of documented professional experience and a long-standing engagement in R&D at EDF R&D since 2006, building on early embedded systems work at Viveris. He holds advanced degrees in electrical engineering and signal processing from Université Paris Sud and a DUT in GEII, reflecting a strong foundation in telecommunications, electronics and signal treatment. Vincent blends applied research and hands-on system development, likely focusing on energy, embedded or telecom systems given his institutional context. His profile suggests steady specialization rather than frequent role changes, indicating deep domain knowledge and continuity in research-driven engineering projects.
1 year of coding experience
Master PRO, Electronique - Traitement de signal, Master PRO, Electronique - Traitement de signal at Université Paris Sud (Paris XI) / University Paris XI
Diplôme universitaire de technologie (DUT), GEII, Diplôme universitaire de technologie (DUT), GEII at Université Paris-Est Créteil (UPEC)
Ingenieur Maître, Génie électrique - Option systèmes télécoms, Ingenieur Maître, Génie électrique - Option systèmes télécoms at Université Paris Sud (Paris XI)
Matter (formerly Project CHIP) creates more connections between more objects, simplifying development for manufacturers and increasing compatibility for consumers, guided by the Connectivity Standards Alliance.
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