Summary
Vinod Sake is a Principal Engineer with nine years of experience in pre-silicon design verification, currently validating Smart NICs at Marvell after leading silicon verification at AMD and Intel. He specializes in SoC-level cache coherency, PCIe and Ethernet interactions, UVM-based testbench development, and emulation of x86 features like QOS and UPI, often writing bare-metal assembly to generate realistic traffic. Comfortable across Verilog/SystemVerilog, UVM, C/C++ and Python, he combines hands-on RTL/debug expertise with coverage-driven verification and timing analysis. Vinod’s background spans ASIC design, behavioral-to-gate-level validation and emulator flows (Veloce), enabling him to bridge protocol, firmware and hardware teams under tight schedules. A computer-hardware enthusiast by trade, he brings both practical lab experience and academic depth from an MS in EEE, plus a track record of shipping complex verification environments for high-performance chips.
9 years of coding experience
8 years of employment as a software developer
High School General Education, High School General Education at Bhashyam Public High School
Master of Science (MS) Electrical and Electronics Engineering, Master of Science (MS) Electrical and Electronics Engineering at Portland State University
Narayana Junior College
Bachelor of Engineering (B.E.) Electrical and Electronics Engineering, Bachelor of Engineering (B.E.) Electrical and Electronics Engineering at Osmania University
English, Telugu, Hindi