Vishnu Ramadas
Research Scholar at University of Wisconsin-Madison
Madison, Wisconsin, United States
Summary
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Senior🎓
Top SchoolVishnu Ramadas is a research-focused engineer specializing in GPU architectures, heterogeneous systems, and high-performance memory subsystems, currently pursuing a PhD at the University of Wisconsin–Madison. With nine years of industry and research experience, he has worked on C++ performance and functional modeling and contributed to SoC and multimedia architecture efforts at Samsung and a GPU architecture stint at NVIDIA. He is an active contributor to the widely used gem5 simulator, adding GPU-specific features like configurable shared-memory latencies, cache bypassing, and robust checkpointing support. His work blends low-level architectural insight with practical tooling that aids accurate simulation and reproducible experiments across GPU/CPU co-designs. Based in Madison, he pairs academic rigor with production experience, often surfacing subtle correctness fixes (e.g., TLB/stat issues and warmup/cooldown semantics) that improve long-running evaluations. Curious and detail-oriented, he focuses on the intersection of microarchitecture and system-level modeling to make performance research more reliable and actionable.
9 years of coding experience
4 years of employment as a software developer
BITS Pilani, Birla Institute of Technology and ScienceDoctor of Philosophy - PhD, Doctor of Philosophy - PhD at University of Wisconsin-Madison
Stackoverflow
1reputation
0reached
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Github Skills (10)
simulations10
simulation10
c-language10
architectures10
main-memory10
cprogramming-language10
gpu10
computer-architecture10
architecture10
open-source9
Programming languages (4)
Github contributions (5)
gem5/gem5
Sep 2022 - Jan 2023
The official repository for the gem5 computer-system architecture simulator.
Role in this project:
Backend Developer
Backend DeveloperContributions:46 reviews, 7 commits, 11 PRs in 3 months
Contributions summary:Vishnu primarily contributed to the gem5 computer-system architecture simulator by adding and configuring various GPU-related features. These contributions included adding configurable latencies for shared memory access, scalar cache paths, and GPU cache bypassing capabilities. The user also addressed issues related to checkpointing and restoration, adding support for features like cache cooldown and warmup, and fixing incorrect TLB stats when FunctionalTLB is used. Additionally, the user added GPUFS checkpointing support for AQL, hsa queue information, GART translations and PM4 queue metadata.
storedsimulationupstreamsimulatorgem5-simulator
v-ramadas/gem5
Sep 2023 - Feb 2025
The official repository for the gem5 computer-system architecture simulator.
Contributions:45 pushes, 19 branches in 1 year 5 months
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