Vladislav Rumiantsev is a Senior Verification Engineer based in Edinburgh with eight years of experience in IC verification and embedded systems, currently advancing chip and IP-level verification at Cirrus Logic. He specializes in SystemVerilog/UVM testbenches, VIP development, functional coverage and SVA, and has led HW/SW co-verification efforts that introduced improved test scenario and bug-tracking flows across teams. Vladislav pairs low-level verification expertise with embedded firmware experience—building ESP32-based connected products and custom BLE solutions—and has driven cross-disciplinary projects from prototype to production. He has a track record of team leadership through roles like Head of Smart Pod for Edinburgh’s Hyperloop team (Electronics Weekly BrightSparks 2018), and he brings practical lab skills (oscilloscopes, signal analysis) combined with verification planning and mentoring of interns. Notably, he blends algorithmic FPGA work and parallel software optimization from earlier LiFi projects with contemporary system-level verification practices.
8 years of coding experience
6 years of employment as a software developer
Master’s Degree, Electrical and Electronics Engineering, 1st Class Honours, Master’s Degree, Electrical and Electronics Engineering, 1st Class Honours at The University of Edinburgh
High School, Engineering, 86%, High School, Engineering, 86% at King's Education Oxford
cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python
Contributions:9 pushes in 1 day
uvmasicpythonvhdlcosimulation
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