Vu Phan
Formal Verification Engineer
Houston, Texas, United States
Summary
👤
Senior🎓
Top SchoolVu Phan is a Formal Verification engineer with 11 years of experience applying formal methods to pre-silicon validation of complex SoC designs. He holds a PhD in Computer Science from Rice University (advised by Moshe Vardi) and has validated two generations of IP at Intel, co-owning cache-coherence fabric features such as ECC, machine-check architecture, and power-management handshakes. Proficient in SystemVerilog, Cadence JasperGold, Synopsys VCS, Python, C++, Java, and Scala, he combines theoretical rigor in algorithms and data structures with practical tooling and automation for FPV benchmarking. Vu has a track record of finding subtle RTL bugs, writing clear reports, and driving fixes across cross-functional teams. Now at Cirrus Logic after a brief stint advising on patents and consulting, he brings both deep research pedigree and hands-on silicon validation experience. An understated strength is his ability to translate formal proofs into actionable RTL fixes and measurable reliability improvements.
11 years of coding experience
4 years of employment as a software developer
Bachelor of Science - BS, Mathematics and Computer Science, Bachelor of Science - BS, Mathematics and Computer Science at Texas Tech UniversityDoctor of Philosophy - PhD, Computer Science, Doctor of Philosophy - PhD, Computer Science at Rice University
Github Skills (57)
team-project10
weighted10
linux9
macos8
translator8
branches8
debian-linux8
driver8
windows8
prolog8
javascript8
translation8
electron8
xor8
algebra7
Programming languages (8)
Github contributions (5)
vuphan314/ShattleBip
Feb 2016 - Jun 2018
Contributions:6 releases, 95 commits, 28 PRs in 2 years 4 months
vuepaulspringteam-project
iensen/LtoASPtranslator
Jun 2015 - Sep 2020
Contributions:1 release, 197 commits, 8 PRs in 5 years 3 months
answertranslationasptranslatorprolog
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