Wei-lin Cheng is a product engineering manager with six years of software and chip-design experience, now leading Legalization/Chip Finishing/ECO teams at Synopsys to enable advanced process nodes. He combines backend engineering skills in Python and JavaScript with practical expertise in databases (MySQL, Redis), Linux tooling, and cloud EC2 to deliver performant, production-grade systems. Previously he accelerated API performance at Trend Micro by 60% through targeted root-cause analysis and cross-team collaboration, and earlier work reduced regression runtimes by over 60% via distributed test execution. Comfortable bridging diverse engineering cultures, he has trained hundreds of designers on best practices and translates complex physical-design constraints into reliable product features. Trained in electrical engineering at USC and NCTU, he blends chip-level domain knowledge with pragmatic software leadership.
6 years of coding experience
13 years of employment as a software developer
Master of Science - MS Electrical Engineering, Master of Science - MS Electrical Engineering at University of Southern California
Bachelor of Science - BS Electrophysics, Bachelor of Science - BS Electrophysics at National Chiao Tung University
Contributions:79 PRs, 61 pushes, 61 branches in 6 months
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Wei-lin Cheng - Product Engineering Manager at Synopsys Inc