Weichung Wu
Sr. Staff Verification Engineer
Hsinchu, Taiwan Province
Summary
👤
Senior🎓
Top SchoolWeichung Wu is a Sr. Staff Verification Engineer with 14 years of experience specializing in reusable, layered UVM testbench architecture for SoC and system verification. He combines OOP-based testbench design and SOLID principles to build scalable, maintainable UVM environments, and mentors teams on bench architecture and methodology. Deep practical expertise spans SystemVerilog, SVA, Verilog simulators, function coverage, shell scripting and Perl, with a strong track record automating verification flows and integrating UVM reporting into SVA checks. At SiFive and prior roles at NXP and Marvell he has driven verification strategies for complex ASIC projects, translating data specs into rigorous verification plans and code. An efficiency-minded engineer, he even extended VIM to improve personal coding and debug productivity, reflecting a pragmatic focus on tooling and developer experience.
14 years of coding experience
17 years of employment as a software developer
Master's degree, Master's degree at National Tsing Hua University
Stackoverflow
1reputation
0reached
1answer
0questions
Github Skills (11)
systemverilog10
syntax-highlighting10
vimscript10
vim9
verilog6
uart6
subscriber6
monitor6
uvm6
find-and-replace1
python1
Programming languages (1)
Github contributions (5)
WeiChungWu/vim-SystemVerilog
Jun 2012 - Dec 2020
SystemVerilog syntax highlight/indent support in vim
Contributions:21 commits, 7 pushes, 4 comments in 8 years 7 months
systemverilogvimsyntax-highlightingvim-pluginsvimscript
WeiChungWu/dotvim
Jun 2012 - Dec 2020
Contributions:31 commits, 7 pushes in 8 years 7 months
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