Weier Wan is a technology leader and CTO based in Palo Alto with eight years of experience translating cutting-edge hardware research into practical AI products. Trained as a Stanford PhD in Electrical Engineering, he led the design and experimental validation of NeuRRAM, a Nature-published RRAM compute-in-memory chip that set records in energy efficiency and reconfigurability for edge inference. He combines deep device- and system-level expertise—from spintronic and memory-device experiments to embedded Android and power-hardware design—with product-minded leadership at AIZIP. His background spans premier research labs and industry moonshot projects, giving him a rare ability to shepherd innovations from lab prototype to deployable edge AI solutions. Colleagues value his focus on efficiency and his knack for making hardware-aware software that squeezes real-world performance out of constrained platforms.
9 years of coding experience
8 years of employment as a software developer
Stanford Ignite, Certificate Program in Innovation and Entrepreneurship, Stanford Ignite, Certificate Program in Innovation and Entrepreneurship at Stanford University Graduate School of Business
Bachelor’s Degree Double Degree in Physics and EECS, Bachelor’s Degree Double Degree in Physics and EECS at University of California, Berkeley
Doctor of Philosophy (Ph.D.) Electrical Engineering, Doctor of Philosophy (Ph.D.) Electrical Engineering at Stanford University
Verilog and Python drivers and APIs for Neurram 48-core chip
Contributions:12 commits, 9 pushes, 1 branch in 1 year 10 months
driverpythonverilog
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