Xi Luo

Middleware Development Engineer at Intel Corporation

San Francisco Bay Area United States
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Summary

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Senior
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Top School
Xi Luo is a middleware development engineer with a decade of experience specializing in high-performance computing, MPI collective operations, and performance analysis. Based in the San Francisco Bay Area, he builds low-latency runtime systems and has a strong track record of optimizing collective communication across CPU, GPU, and FPGA platforms. His work spans industry and national labs—contributing FPGA offload modules for Realm at SLAC and developing autotuned, topology-aware collective frameworks in Open MPI during his PhD research, including award-winning results at scale. Xi combines systems-level C/C++ expertise with practical Python tooling for profiling and in-situ analytics, and he has reduced autotuning time and improved model accuracy to within 10% of real performance in simulator validations. Notably, he designed lock-free intra-node memory pools and novel cost models that materially improved MPI_Bcast and MPI_Allreduce performance on thousands of cores. He brings a research-driven approach to production middleware, translating academic innovations into deployable runtime components.
code10 years of coding experience
job8 years of employment as a software developer
bookBachelor of Science - BS, Computer Science, Bachelor of Science - BS, Computer Science at Sichuan University
bookMaster of Science - MS, Computer Science, Master of Science - MS, Computer Science at Stevens Institute of Technology
bookDoctor of Philosophy - PhD, Computer Science, Doctor of Philosophy - PhD, Computer Science at University of Tennessee, Knoxville
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Github Skills (18)

parallelization10
legion10
fortran10
mpi10
cluster-computing10
hpc10
openmpi10
manifold10
petsc10
co-simulation10
system-programming9
deep-learning8
machine-learning8
parallel8
pytorch8

Programming languages (3)

C++CPython

Github contributions (5)

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dycz0fx/ompi

Apr 2016 - Sep 2023

Open MPI main development repository
Contributions:154 pushes, 25 branches in 7 years 6 months
mpi
dycz0fx/mpich

Sep 2022 - Aug 2024

Official MPICH Repository
Contributions:251 pushes, 14 branches in 1 year 11 months
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Xi Luo - Middleware Development Engineer at Intel Corporation