Xiangwei Li
Senior Frontend Engineer at Bitdeer (NASDAQ: BTDR)
Singapore
Summary
👤
Senior🎓
Top SchoolXiangwei Li is a Senior Staff Engineer in system architecture at HiSilicon with nine years of hands-on experience designing AI cores, FPGA accelerators, and high-performance digital systems. He specializes in micro-architecture modeling and full-custom circuit design to improve PPA, and has designed versatile processing elements that support both fixed- and floating-point arithmetic as well as efficient systolic accelerators for high-order FIR and matrix-vector workloads. His background spans industry and academia—from automotive FMCW radar implementations on Xilinx RFSoC and Kria SOMs to FPGA-based deep learning, quantization, and HLS-driven AI chip development—anchored by a PhD in Computer Engineering from Nanyang Technological University. Based in Singapore, he combines research rigor with production-focused engineering, often translating systolic array concepts and RISC-like ISAs into deployable accelerators. Less obvious: he repeatedly bridges toolchains (PYNQ, Vitis, Vivado) and custom silicon flows, making him effective at taking algorithms through to silicon-aware implementations.
10 years of coding experience
7 years of employment as a software developer
The University of Hong Kong (HKU)Doctor of Philosophy (PhD) Computer Engineering, Doctor of Philosophy (PhD) Computer Engineering at Nanyang Technological University Singapore
Chinese, English
Github Skills (16)
zynq10
xilinx10
vitis9
risc-v8
hardware8
python8
gpu7
machine-learning7
deep-learning7
inference6
ai6
numpy5
neural-network5
tensor3
gpu-acceleration3
Programming languages (4)
Github contributions (5)
louislxw/FAM
May 2020 - Jul 2022
Contributions:20 commits, 20 pushes, 1 branch in 2 years 1 month
louislxw/pe_array
May 2020 - Aug 2021
A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as SCD and CNNs.
Contributions:206 commits, 208 pushes, 1 branch in 1 year 3 months
risc-vxilinxzynq
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