Xiao Dai - Software Engineer at Meta

Xiao Dai

Software Engineer at Meta

New York, New York, United States

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Summary

🤩

Rockstar

🎓

Top School

Xiao Dai is a software engineer with nine years of experience who blends systems-level programming and hardware-aware tooling, currently advancing infrastructure at Meta while completing an MEng in Computer Science at Cornell Tech. A University of Toronto computer engineering graduate, she is fluent in Python, Java, C/C++, Verilog, Assembly, and SQL, and has applied that mix to both industry internships (Intel, Thales) and academic research. Her open-source contributions include backend work on the well-known Verilog-to-Routing (VTR) FPGA CAD flow—fixing routing logic, SINK handling, and segmentation faults—which reflects her attention to robustness in low-level code. As an experienced coding instructor, she pairs clear technical communication with hands-on debugging skills, making her effective at mentoring and complex problem solving across software and hardware domains.

9 years of coding experience

1 year of employment as a software developer

Bachelor of Applied Science - BASc, Computer Engineering, Bachelor of Applied Science - BASc, Computer Engineering at University of Toronto

Master of Engineering - MEng, Computer Science, Master of Engineering - MEng, Computer Science at Cornell University

Master of Engineering - MEng, Computer Science, Master of Engineering - MEng, Computer Science at Cornell Tech

English, Chinese, French

Github Skills (6)

fpga10

url-routing10

verilog10

eda10

cprogramming-language9

c-language9

Programming languages (2)

C++HTML

Github contributions (5)

verilog-to-routing/vtr-verilog-to-routing

Jun 2020 - Sep 2020

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Role in this project:

Back-end Developer

Contributions:62 commits, 5 PRs, 67 pushes in 2 months

Contributions summary:Xiao contributed to the VTR (Verilog to Routing) project, focusing on modifying scripts and source code related to the architecture files and routing process. Their contributions included updating the download script for Titan benchmarks to avoid replacing architecture files, and modifications to the routing code, specifically around the handling of SINK nodes and net pin indices. The user made adjustments to the code for removing one-LUTs and fixing segmentation fault issues.

vtrcadedaplacementsynthesis

jishengx97/FullMonteWeb

Sep 2020 - Jan 2022

A web-application for running and visualizing the results of the FullMonte simulator

Contributions:90 PRs, 166 pushes, 24 branches in 1 year 4 months

simulatorvisualizingweb-application

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