Xifan Tang
Chief Technology Officer at Rapid Flex
Los Gatos, California, United States
Summary
🤩
Rockstar🎓
Top SchoolXifan Tang is a technology leader and researcher with 11 years of experience bridging advanced FPGA architecture research and product engineering, currently serving as CTO of Rapid Flex in the San Jose area. He earned a PhD from EPFL and brings deep expertise in EDA tools, circuit modeling, and RRAM-based FPGA architecture, with 24 publications and a US patent to his name. Xifan has held research and engineering roles at University of Utah and RapidSilicon, and contributed substantive back-end work to the widely used open-source VTR Verilog-to-Routing project, improving core routing resource data structures and robustness. He combines academic rigor with hands-on system design—tackling clock tree synthesis, power grids, and novel memory-centric FPGA fabrics—and has steered open-source governance as a former board member of the Open-Source FPGA Foundation. Based in Los Gatos, he is known for translating cutting-edge research into practical tooling and silicon-capable architectures that shorten the path from paper to prototype.
11 years of coding experience
13 years of employment as a software developer
High school attached to Shanghai Jiao Tong Univ.Bachelor, Micro-Electronics, Bachelor, Micro-Electronics at Fudan UniversityMaster's degree, Electrical Engineering, Master's degree, Electrical Engineering at Ecole polytechnique fédérale de LausannePhD degree, Electrical and Electronics Engineering, PhD degree, Electrical and Electronics Engineering at École polytechnique fédérale de Lausanne
English, Chinese
Github Skills (11)
fpga10
develop10
c-language10
cprogramming-language10
eda9
data-structure9
debug9
data-structures9
url-routing9
debugging9
refactoring8
Programming languages (4)
Github contributions (5)
verilog-to-routing/vtr-verilog-to-routing
Aug 2019 - Jan 2023
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Role in this project:
Back-end Developer
Back-end DeveloperContributions:360 reviews, 464 commits, 78 PRs in 3 years 6 months
Contributions summary:Xifan implemented core functionality for a new Routing Resource (RR) Graph class in the VTR-Verilog-to-Routing project. Their work focused on creating the class interface, implementation, and sanity checking infrastructure to encapsulate the inter-block FPGA routing network. Additionally, the user addressed several bugs, including potential null pointer dereferences within the check_rr_graph_obj and also created a function that adds more comments, fixes type conversions and added a method called set_node_type() to allow users to modify the type for a specific RRNodeId. The primary focus was on refining the internal data structures of the project.
vtrcadedaplacementsynthesis
tangxifan/tangxifan-eda-tools
Mar 2015 - Mar 2022
Contributions:386 commits, 17 PRs, 408 pushes in 7 years 1 month
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