Summary
Xin Ouyang is a senior R&D engineering professional with 10 years of experience specializing in std-cell and library characterization, signoff extraction flows, and analog IC design. Based in San Diego and currently at Synopsys, Xin blends hands-on Cadence Virtuoso analog design and SPICE simulation with deep expertise in Synopsys Siliconsmart and StarRC tools to meet timing, power, and area targets across advanced nodes. He pairs a solid understanding of transistor device physics with practical layout collaboration to produce dense, process-tolerant designs and robust gate/transistor-level timing analysis. Xin also scripts and automates flows in Tcl, C-shell and Python, enabling faster characterization and rapid prototyping for high-profile customers like Qualcomm. An MEng graduate from the University of Pennsylvania, he has a track record of translating microarchitecture and functional specs into validated schematics and signoff-ready libraries. Colleagues note his blend of field-support pragmatism and deep technical debugging skills that bridge EDA product capabilities and customer deliverables.
10 years of coding experience
2 years of employment as a software developer
BSEE Power System and Automation, BSEE Power System and Automation at North China Electric Power University
Master of Engineering (MEng) Electrical Engineering, Master of Engineering (MEng) Electrical Engineering at University of Pennsylvania
English, Chinese