Xin Wang is a Senior IP Verification Engineer with nine years of semiconductor experience, currently driving verification for Intel’s Xeon-class SoCs. Skilled in SystemVerilog, Verilog and UVM methodology, Xin has deep hands-on expertise with high-speed interfaces including PCIe and storage/networking protocols developed across Marvell and Intel. He combines RTL coding and SOC-level verification with practical knowledge of ASIC flows and tools (VCS, DC, Spyglass, CDC, STA), enabling robust pre-silicon validation and quality assurance. Xin also contributed early core-native interface code to the widely used wasm-micro-runtime project, reflecting an openness to low-level systems and open-source collaboration outside traditional ASIC work. Based in California, he leverages an MSEE from the University of Michigan to bridge rigorous academic grounding with pragmatic engineering delivery. Colleagues rely on him for thorough, interface-focused verification that anticipates system-level integration challenges.
9 years of coding experience
5 years of employment as a software developer
Master, Electrical Engineering, Master, Electrical Engineering at University of Michigan
Contributions:5 reviews, 68 commits, 85 PRs in 3 years 6 months
Contributions summary:Xin appears to be involved in the initial development of the WebAssembly Micro Runtime (WAMR) project. Their primary contribution includes the first version of the project, with code changes focused on core functionalities and native interface components within the `core/iwasm/lib/native-interface` directory, particularly `attr-container.c`. These changes suggest the implementation of fundamental components for the runtime environment.
Contributions:12 commits, 8 PRs, 10 pushes in 4 years 6 months
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