Xinxin Wang is a postdoctoral scholar in Palo Alto specializing in in-memory computing architectures for AI acceleration, with seven years of experience bridging device-level non-idealities and system-level DNN performance. She designed a tiled architecture for DNN inference, quantified the effects of bitcell imperfections and ADC quantization on model accuracy, and proposed practical bitcell requirements and multi-range ADC schemes to reduce computational error. Her work balances layer-level throughput via weight-array duplication and ADC multiplexing, and includes end-to-end performance analyses (latency, power, capacity, TOPS/W) for ResNet50, MobileNet, Inception-V4, and Transformer models. At Stanford following a PhD from the University of Michigan and internship experience validating RRAM-based accelerators at Applied Materials, she blends hands-on lab validation, architecture-aware training, and AI simulation—bringing both experimental rigor and system-level insight to hardware-aware ML.
7 years of coding experience
Doctor of Philosophy - PhD, Electrical Engineering and Computer Science, Doctor of Philosophy - PhD, Electrical Engineering and Computer Science at University of Michigan
Bachelor of Science - BS, Microelectronics Science and Engineering, Bachelor of Science - BS, Microelectronics Science and Engineering at Peking University
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Xinxin Wang - Postdoctoral Scholar at Stanford University