Xiongliang Lai
Analog Design Engineer at MeritSilicon Ltd.
Ottawa, Ontario, Canada
Summary
👤
Senior🎓
Top SchoolXiongliang Lai is an analog design engineer with nine years of deep experience in high-speed SerDes, DDR PHY IO architecture and RF/MMIC development across leading semiconductor and startup environments. He has delivered products from 28–56 GHz PLLs and ADPLLs to >28GSps SAR ADCs and 224/448Gbps SerDes links, and has led teams to port LPDDR5x and ONFI5.1 PHY IOs. Skilled in Cadence Virtuoso, SpectreRF, Calibre and EM tools, he combines hands-on circuit design (PLL/DLL, ADC/DAC, Tx/Rx) with signal-integrity expertise like Smith-chart impedance matching and equalization tuning. Xiongliang pairs IP-level architectural insight with practical testbench and lab experience—oscilloscopes, network and spectrum analyzers—making him effective as both an individual contributor and small R&D leader. He has published work on low-noise amplifiers and jitter budgeting, reflecting a research-to-product track record across TSMC, Synopsys, AMD and startups. Based in Ottawa, he brings a rare blend of system-architecture thinking and hands-on analog/RF craft, often applying mathematical rigor from his advanced degrees to optimize channel and IO performance.
9 years of coding experience
18 years of employment as a software developer
Master Mathematics, Master Mathematics at Wichita State UniversityToronto Metropolitan UniversityMaster Analog VLSI, Master Analog VLSI at Brigham Young University
Github Skills (4)
apache6
java6
big-data3
apache-iceberg1
Programming languages (1)
Github contributions (5)
xiongliang1989/Spring-springmvc-mybatis-for-user-login
Jul 2017 - Jan 2018
Contributions:4 commits, 4 pushes, 1 branch in 6 months
xiongliang1989/test
Dec 2016 - Mar 2017
Contributions:13 pushes, 2 branches in 3 months
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