Xuxin Zeng
Deep Learning Software Engineer at Intel Corporation
New Jersey, United States
Summary
🤩
Rockstar🎓
Top SchoolXuxin Zeng is a deep learning software engineer based in New Jersey with five years of experience bridging biomedical signal/image processing research and production-grade ML infrastructure. At Intel since 2020, Xuxin has translated low-level performance work into practical gains, notably contributing int8 SSE41 depthwise convolution layouts to the high-profile oneDNN library. Their background combines academic research in robotics and biomedical engineering with hands-on systems work—building camera-to-robot vision pipelines for industrial sorting and obstacle-avoidance algorithms for climbing robots. Comfortable across C++/backend optimizations and data-driven biomedical analysis, Xuxin excels at turning algorithmic insight into efficient, deployable code. A pragmatic collaborator, they bring both research rigor and production discipline to performance-sensitive ML problems.
5 years of coding experience
4 years of employment as a software developer
Bachelor's degree, Biomedical/Medical Engineering, 3.2, Bachelor's degree, Biomedical/Medical Engineering, 3.2 at Shenzhen UniversityMaster's degree, Biomedical/Medical Engineering, Master's degree, Biomedical/Medical Engineering at Rutgers University
Github Skills (17)
c-language10
edn10
deep-neural-networks10
neural-network10
cprogramming-language10
architecture9
computer-architecture9
intel9
standard-library9
x869
cpu-architecture9
deeplearning-ai9
deep-learning9
common-library9
x86-649
Programming languages (1)
Github contributions (3)
uxlfoundation/oneDNN
Aug 2020 - Jan 2023
oneAPI Deep Neural Network Library (oneDNN)
Role in this project:
Backend Developer
Backend DeveloperContributions:50 reviews, 155 commits, 41 PRs in 2 years 5 months
Contributions summary:Xuxin primarily contributed to the oneAPI Deep Neural Network Library (oneDNN) by implementing new weights layouts for int8 SSE41 depthwise convolution. They modified several source files to incorporate support for these new layouts, including `cpu_reorder.cpp`, `simple_reorder.hpp`, `dnnl_debug_autogenerated.cpp`, `c_types_map.hpp`, `dnnl_types.h`, and `tests/benchdnn/dnnl_debug_autogenerated.cpp`. The contributions focused on expanding the library's capabilities to optimize for int8 operations and SSE41 architecture.
bfloat16sse41avx512openmpopencl
xuxinzen/xbyak
Mar 2022 - Mar 2022
a JIT assembler for x86(IA-32)/x64(AMD64, x86-64) MMX/SSE/SSE2/SSE3/SSSE3/SSE4/FPU/AVX/AVX2/AVX-512 by C++ header
Contributions:1 branch in 1 day
avxavx-512ia-32avx2ssse3
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