Summary
Yang Jiao is a chip packaging technologist with a Ph.D. in chemical engineering and eight years of hands-on experience designing porous materials, electrodes, graphene composites, membranes, and heterogeneous catalysts. He has deep expertise in semiconductor assembly and test materials, leading materials integration for backend test modules, SMT and wafer prep, and developing TIMs, pogo pins, test sockets, underfills, and solder processes. His background pairs advanced materials R&D and characterization—viscoelastic properties, failure analysis, and root-cause investigations—with practical process pathfinding that directly improved test reliability and product validation. He has held progressive packaging roles at Intel and Google, often bridging lab-scale materials science with high-volume manufacturing constraints. Based in San Jose, he combines academic rigor from Georgia Tech with startup and venture exposure, giving him both analytical depth and product-focused judgment. Colleagues rely on him for tough failure analyses and for translating novel material concepts into robust assembly and test solutions.
8 years of coding experience
11 years of employment as a software developer
Doctor of Philosophy (Ph.D.) Chemical Engineering, Doctor of Philosophy (Ph.D.) Chemical Engineering at Georgia Institute of Technology
Bachelor of Science (BS) Chemical Engineering, Bachelor of Science (BS) Chemical Engineering at Tianjin University
English, Chinese