Yangyu Chen is a Silicon Validation Engineer at Apple with 11 years of experience bridging computer architecture, RTL validation, and software tooling. He holds strong academic credentials from Georgia Tech and the University of Washington and has driven research in network-on-chip and domain-specific architecture as a Grad Research Assistant. Yangyu has practical chip and CPU experience from multiple roles at Apple and Rivos, where he built RTL performance validation infrastructure and correlated RTL behavior to performance models. He is fluent in C, Python, SystemVerilog and assembly, and has a track record of shipping test suites and developer tools that make hardware features more accessible. An open-source enthusiast and former Ph.D. student focused on architecture-software co-design, he combines rigorous research thinking with hands-on debugging across the full stack of silicon validation. Based in Austin, he brings rare cross-disciplinary experience from bio-robotics ML work to large-scale CPU validation.
11 years of coding experience
4 years of employment as a software developer
Bachelor of Science - BS, Electrical and Computer Engineering, 3.87 - Magna Cum Laude, Bachelor of Science - BS, Electrical and Computer Engineering, 3.87 - Magna Cum Laude at University of Washington
Master's degree, Electrical and Computer Engineering, 4.0, Master's degree, Electrical and Computer Engineering, 4.0 at Georgia Institute of Technology
Contributions:1 review, 78 commits, 3 PRs in 1 year
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