Yashas Dattatreya is a silicon engineer with eight years of hands-on experience in microarchitecture and RTL design, currently working on silicon at Meta. He holds an M.S. in Computer Engineering from USC and has built production-grade RTL accelerators and uArch blocks across startups and industry internships at Rivos, AMD, and Google. Yashas combines low-level expertise—from writing assembly and C/C++ to RTL and performance characterization—with practical FPGA achievements, including a 2.5 TFLOPS cached matrix-multiplication accelerator on Stratix 10 and a 204.8 GFLOPS Arria 10 implementation. He’s an educator and mentor who supported computer systems courses at USC, reflecting an ability to communicate complex hardware concepts clearly. Based in California, he brings a systems-first mindset and a track record of turning architectural ideas into high-throughput, synthesizeable implementations.
8 years of coding experience
4 years of employment as a software developer
B.Tech Computer Science and Engineering, B.Tech Computer Science and Engineering at PES University
Master's degree Computer Engineering, Master's degree Computer Engineering at University of Southern California
10th, 10th at Mahajana Public School
Pre University Computer Science Mathematics Physics and Chemistry, Pre University Computer Science Mathematics Physics and Chemistry at Manasarovar Pushkarini Vidyashram PU College (Deeksha integrated)
Contributions:3 PRs, 81 pushes, 13 branches in 4 years 5 months
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