Yeong Wang
Principle Design Engineer at Broadcom Inc.
California, United States
Summary
🤩
Rockstar🎓
Top SchoolYeong Wang is a Principal Design Engineer based in California with seven years of focused experience in RTL-based ASIC design, SOC integration, and FPGA prototyping. He has deep hands-on expertise translating DSP algorithms from C/Matlab into Verilog, designing SOC peripherals and testbenches, and driving timing closure through to tapeout. At Broadcom he leads complex chip projects, building on earlier work designing DFE/DEMOD/FSK and AMBA-based SOC subsystems for satellite TV at Maxlinea. Beyond silicon, he contributes backend Java work to an objectivesql project, showing an ability to extend software tooling and unit-test ANSI SQL features. Known for bridging algorithmic design and pragmatic system verification, he combines low-level RTL rigor with system-level validation and emulation skills.
7 years of coding experience
6 years of employment as a software developer
University of Southern California
Github Skills (7)
javas10
java-api10
sql10
java10
orm9
activerecord9
unit-testing8
Programming languages (8)
Github contributions (5)
braisdom/ObjectiveSql
Jul 2020 - Aug 2022
Writing SQL using Java syntax
Role in this project:
Back-end Developer
Back-end DeveloperContributions:189 commits, 20 PRs, 1041 pushes in 2 years 1 month
Contributions summary:Yeong primarily contributed to adding and modifying core functionalities within the `objectivesql` project, focusing on Java syntax for SQL generation. Their work included the implementation of SQL functions, modifying code related to transactional aspects, and adding unit tests for ANSI functions. The user made significant changes to existing files, adding new functionality to the project. They enhanced the project by implementing and expanding the SQL feature set.
java-ormmysqlrapid-developmentjsonbsql
braisdom/JDrucker
Apr 2019 - Oct 2019
Contributions:3 commits, 106 pushes, 2 branches in 5 months
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