Yi Cao
FPGA Engineer at Susquehanna International Group
Parsippany-Troy Hills, New Jersey, United States
Summary
👤
Senior🎓
Top SchoolYi Cao is an FPGA engineer with over a decade of experience designing low-latency, high-throughput digital systems across ASIC and FPGA platforms, currently developing FPGA solutions for high-frequency trading. He led RTL ownership for Qualcomm’s 5G NR LDPC decoder and has deep expertise in DSP, wireless standards (4G/5G, WiFi, Bluetooth), and multimedia codecs, bringing practical tradeoff decisions across performance, power, area, and frequency. Comfortable across the toolchain—from Verilog/VHDL, Synopsys Design Compiler and timing closure to Xilinx/Altera toolflows and embedded Linux/U-Boot—he routinely turns conceptual algorithms into silicon and production firmware. His background includes networked media (IEEE 802.1 AVB), 1G/10G Ethernet interfaces, and hands-on experience with MicroBlaze/Nios II soft cores and microcontrollers. A PhD-trained engineer who has multiple patents and publications, he pairs meticulous debugging and documentation skills with a penchant for squeezing deterministic latency out of complex hardware designs.
10 years of coding experience
14 years of employment as a software developer
Bachelor Electronic Engineering and Information Science, Bachelor Electronic Engineering and Information Science at University of Science and Technology of ChinaPhD Electrical and Computer Engineering, PhD Electrical and Computer Engineering at Syracuse University
Github Skills (3)
relationship7
soa4
citation4
Github contributions (5)
caoyielliot/Survival-Social-Network-on-Chip-
May 2016 - May 2016
Contributions:1 commit, 1 branch in 1 day
caoyielliot/Java-smart-phone
Mar 2016 - May 2016
Contributions:5 pushes, 1 branch in 2 months
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