Yi-min Lin
Digital Design Engineer at Google
San Jose, California, United States
Summary
👤
Senior🎓
Top SchoolYi-min Lin is a Digital Design Engineer with 9 years of experience designing high-performance ECC and storage controller IPs for SSDs and wireless SoCs, currently contributing at Google from San Jose. He brings deep algorithm-to-RTL expertise in BCH, RS, LDPC and TPC codes, combined with practical NAND flash, FTL and 3D XPoint memory controller experience across Micron, Intel and SK Hynix. His background spans both communications baseband (60GHz, LTE/5G, Bluetooth) and storage verification, including power analysis and FPGA prototyping to characterize LDPC error floors. A PhD-trained codec implementer, he has a track record of tape-outs and low-power, area-efficient encoder/decoder IPs that converted academic soft-decoding research into production silicon. Notably, he and his teams shipped controller back-end logic for Micron’s first 3D XPoint SSD and led SK Hynix’s first in-house LDPC implementation, reflecting a rare blend of research, silicon bring-up, and product delivery.
9 years of coding experience
8 years of employment as a software developer
Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering, Doctor of Philosophy (Ph.D.), Electrical and Electronics Engineering at National Chiao Tung UniversityBachelor of Science (BS), Electrical and Electronics Engineering, Bachelor of Science (BS), Electrical and Electronics Engineering at National Tsing Hua University
Chinese, English
Github Skills (11)
authenticity9
photo9
verifiable9
latex7
xelatex7
overleaf6
python5
compiler2
css1
javascript1
google-sheets-api1
Programming languages (6)
Github contributions (5)
vincent10400094/email-verification
Mar 2017 - Apr 2017
Contributions:20 commits, 19 pushes, 1 branch in 3 days
vincent10400094/INFOR-Moodle
May 2017 - May 2017
Contributions:68 commits, 55 pushes, 1 branch in 15 days
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