Yinan Xu
Assistant Professor at Institute of Computing Technology, Chinese Academy of Sciences
Beijing, China
Summary
🤩
Rockstar🎓
Top School
Top expert inDigital Hardware Design and Verification
Yinan Xu is an Assistant Professor and PhD-trained computer system architect with nine years of hands-on experience designing and optimizing high-performance RISC-V processors. Based in Beijing at the Institute of Computing Technology, Chinese Academy of Sciences, he has made substantive backend and system-architecture contributions to prominent open-source projects like Rocket Chip and XiangShan, touching RVC decoding, CSR/hypervisor exception handling, PTW, commit/store units, and load-store queues. His work blends low-level ISA/exception semantics with microarchitectural performance tuning, demonstrating both specification-aligned changes and pragmatic resource-optimization. Colleagues describe him as someone who pairs rigorous research instincts with the practical drive reflected in his GitHub motto: "Life is short, work hard."
9 years of coding experience
Bachelor Computer Science and Technology, Bachelor Computer Science and Technology at University of Chinese Academy of SciencesPhD Computer System Architecture, PhD Computer System Architecture at Institute of Computing Technology, Chinese Academy of Sciences
Github Skills (18)
hardware-designs10
risc-v10
scala10
performance-optimization10
chisel10
rt10
computer-architecture9
architecture9
architectures9
system9
hdl9
rocket-chip8
cprogramming-language8
exception-handling8
c-language8
Programming languages (12)
Github contributions (5)
OpenXiangShan/XiangShan
Jun 2020 - Jan 2023
Open-source high-performance RISC-V processor
Role in this project:
Back-end Developer
Back-end DeveloperContributions:1 release, 597 reviews, 1997 commits in 2 years 7 months
Contributions summary:Yinan's contributions center on modifying and extending the architecture of a high-performance RISC-V processor. They implemented features for the processor's commit and store unit by modifying a data module, improving resource allocation and optimizing issue timing. The user's code changes demonstrate a focus on the performance and structural improvements to the system's core backend components, which includes contributions to load-store queue and function units.
risc-vcpuriscvperformancemicroarchitecture
chipsalliance/rocket-chip
Dec 2022 - Dec 2022
Rocket Chip Generator
Role in this project:Back-end Developer & System Architect
Back-end Developer & System ArchitectContributions:4 reviews, 1 commit, 8 PRs in 1 day
Contributions summary:Yinan primarily contributed to the Rocket Chip Generator by modifying core system components related to RISC-V architecture, compressed instructions, and exception handling. Their work involved altering the RVC decoder for compressed move instructions, which required modifying the decoding logic and adding a configuration option. The user also worked on CSR configurations, including adding functionality for delegable hypervisor exceptions and adding the mconfigptr to align with the Priv spec. Further contributions include changes to Page Table Walker (PTW).
rtlriscvchipchiselscala
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.