elike
Pudong, China
Summary
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SeniorYiwei Yang is a founder and fourth-year Ph.D. candidate in Computer Science at UC Santa Cruz specializing in hardware-software co-design for next-generation memory and heterogeneous systems. He leads research on Slug Architecture leveraging CXL and UCIe to offload memory bus control and accelerate data access across distributed endpoints, and he applies that work commercially through zett.ai to redefine AI infrastructure with fully disaggregated, heterogeneous architectures. With a decade of engineering experience that includes AI compiler and production engineering internships at Oxmiq Labs and Jump Trading, he bridges low-level systems innovation and practical deployment. Based in California and Shanghai, he combines academic rigor with startup pragmatism and a keen interest in turning architectural research into marketable infrastructure. Notably, his approach emphasizes adaptive software that provides semantic hints to specialized hardware while gracefully falling back when acceleration isn’t possible.
10 years of coding experience
Github Skills (6)
verilog7
verilator6
systemc5
systemverilog5
cpp5
ghost-blog1
Programming languages (2)
Github contributions (5)
elike-ypq/elike-ypq.github.io
Apr 2021 - Jun 2024
Contributions:78 pushes, 1 branch, 1 issue in 3 years 2 months
elike-ypq/elike
Nov 2016 - Jan 2018
Contributions:25 commits, 27 pushes, 1 branch in 1 year 1 month
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