Yo-chi Lee
Senior ISP Design Engineer at 聯發科技
Taipei, Taiwan
Summary
👤
Senior🎓
Top SchoolYo-Chi Lee is a Senior ISP Design Engineer based in Taipei with eight years of hands-on experience in ISP RTL design, SOC-level integration and verification at MediaTek. He combines academic depth in Electronic Design Automation—where his master’s research produced optimized ECO algorithms and an equivalence-checking solver—with practical EDA scripting and silicon-oriented DV work. Proficient in Verilog/SystemVerilog, C/C++, Python and Perl, he bridges algorithmic EDA research and production RTL/CPU verification flows using tools like VCS, Verdi, JasperGold and PowerArtist. Notably, his student team built a resource-aware ECO tool that ranked in the top 10 worldwide at the ICCAD CAD contest, reflecting a knack for turning formal methods into efficient, real-world tools.
8 years of coding experience
8 years of employment as a software developer
Master of Science (M.S.) Electrical Engineering, Master of Science (M.S.) Electrical Engineering at National Taiwan University
Chinese, EnglishGithub contributions (5)
miamirobin/2017CAD_Contest_ProblemA
Jan 2018 - May 2018
Contributions:10 commits, 7 pushes, 2 branches in 3 months
miamirobin/2017Fall_LSV
Jan 2018 - Jan 2018
Contributions:7 commits, 6 pushes, 2 branches in 1 day
Find and Hire Top DevelopersWe’ve analyzed the programming source code of over 60 million software developers on GitHub and scored them by 50,000 skills. Sign-up on Prog,AI to search for software developers.